ENABLERX=DISABLED, ENABLETX=DISABLED, DMATX=NOT_TRIGGERED, DMARX=NOT_TRIGGERED
FIFO configuration and enable register.
| ENABLETX | Enable the transmit FIFO. 0 (DISABLED): The transmit FIFO is not enabled. 1 (ENABLED): The transmit FIFO is enabled. |
| ENABLERX | Enable the receive FIFO. 0 (DISABLED): The transmit FIFO is not enabled. 1 (ENABLED): The transmit FIFO is enabled. |
| SIZE | FIFO size configuration. This is a read-only field. 0x1 = FIFO is configured as 8 entries of 16 bits. 0x0, 0x2, 0x3 = not applicable to SPI. |
| DMATX | DMA configuration for transmit. 0 (NOT_TRIGGERED): DMA is not used for the transmit function. 1 (TRIGGERED): Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. |
| DMARX | DMA configuration for receive. 0 (NOT_TRIGGERED): DMA is not used for the receive function. 1 (TRIGGERED): Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. |
| EMPTYTX | Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. |
| EMPTYRX | Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. |